#![no_std]


pub mod export {
    pub use cortex_m;
    pub use cortex_m_rt;
    pub mod device {
        pub use stm32f4::stm32f407::*;
    }
}

mod f4;

pub mod driver {
    pub use crate::f4::*;
}


pub use derive_lib::DmaConfig;
pub use derive_lib::GpioConfig;
pub use derive_lib::UartConfig;
pub use derive_lib::AdcConfig;


// #[derive(GpioConfig)]
// #[gpio(init = "init",
//     io(name = "t0", io = "PA0", mode = "OUT", otype = "PP", set, reset, toggle),
//     io(name = "t1", io = "PA13", mode = "IN", pupd = "UP", read, exti_down, exti_up),
//     io(name = "t2", io = "PA3", mode = "AF", otype = "PP", af = "AF15", set, reset, toggle),
//     io(name = "t4", io = "PA15", mode = "AF", otype = "PP", af = "AF8"),
//     io(name = "t5", io = "PC3", mode = "OUT", otype = "OD", level = true, set, reset, read),
// )]
// struct T;

fn test() {
    let pa = unsafe { stm32f4::stm32f407::GPIOA::steal() };
    let rcc = unsafe { stm32f4::stm32f407::RCC::steal() };

    rcc.apb2enr().modify(|_, w| w.tim1en().enabled());
    let tim = unsafe { stm32f4::stm32f407::TIM1::steal() };
    tim.cr1().reset();
    tim.arr().write(|w| w.arr().set(84 - 1));

    let uart = unsafe { export::device::USART1::steal() };
    uart.sr().read().idle().is_idle();
    uart.dr().read();

    let dma = unsafe { export::device::DMA1::steal() };
    let n = dma.st(0).ndtr().read().ndt().bits();
    dma.lisr().read().tcif0().is_complete();
}

#[derive(Debug, DmaConfig)]
#[dma(
    init = "init",
    dma = 1,
    stream = 2,
    ch = 3,
    size = 32,
    dir = "periph_to_mem",
    minc,
    circ,
    tcie,
    priority = "high"
)]
struct T;

#[derive(Debug, UartConfig)]
#[uart(init = "init", name = "USART1", baud_rate = 115200)]
struct T2;

#[derive(Debug, AdcConfig)]
#[adc(init = "init", adc = "ADC1", 
    ch = 1, ch = 10, ch = 2, ch = 5, ch = 14
)]
struct T3;
